library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ap_a_03 is
end entity ap_a_03;


architecture test of ap_a_03 is

begin

  ap_a_03_a : block

    signal sample : natural range 0 to 100;
    signal ready, limit_exceeded, status : bit;

  begin

    -- code from book

    status <= ready and not limit_exceeded;

    -- end code from book

  end block ap_a_03_a;

  --

  ap_a_03_b : block

    signal addr : bit_vector(1 downto 0);
    signal request, request_a, request_b, request_c, request_d : bit;

  begin

    -- code from book

    with addr(1 downto 0) select
      request <=  request_a when "00",
                  request_b when "01",
                  request_c when "10",
                  request_d when "11";

    -- end code from book

  end block ap_a_03_b;

  --

  ap_a_03_c : block

    signal addr : bit_vector(1 downto 0);
    signal request, request_a, request_b, request_c, request_d : bit;

  begin

    -- code from book

    request <= request_a when addr(1 downto 0) = "00" else
               request_b when addr(1 downto 0) = "01" else
               request_c when addr(1 downto 0) = "10" else
               request_d when addr(1 downto 0) = "11";

    -- end code from book

  end block ap_a_03_c;

  --

  ap_a_03_d : block

    signal sample_byte : unsigned(7 downto 0);
    signal data_bus : unsigned(15 downto 0);
    signal sample_enable : std_logic;

  begin

    -- code from book

    data_bus <= resize(sample_byte, 16) when std_match(sample_enable, '1') else
                "ZZZZZZZZZZZZZZZZ";

    -- end code from book

  end block ap_a_03_d;

  --

  ap_a_03_e : block

    subtype byte is unsigned(7 downto 0);

    signal data, sample : byte;
    signal read_enable, parity, status, ready, limit_exceeded : std_logic;

    function calc_parity ( sample : byte ) return std_logic is
    begin
      return '0';
    end function calc_parity;

  begin

    -- code from book

    read_sample : process ( read_enable, sample, limit_exceeded, ready )
    begin
      if std_match(read_enable, '1') then
        data <= sample;
        parity <= calc_parity(sample);
        status <= ready and not limit_exceeded;
      else
        data <= "ZZZZZZZZ";
        parity <= 'Z';
        status <= 'Z';
      end if;
    end process read_sample;

    -- end code from book

  end block ap_a_03_e;

  --

  ap_a_03_f : block

    signal a, b, c, sum : integer;
    signal sel : bit;

  begin

    -- code from book

    adder : process ( sel, a, b, c )
      variable operand : integer;
    begin
      if sel = '1' then
        operand := a;
      else
        operand := b;
      end if;
      sum <= operand + c;
    end process adder;

    -- end code from book

  end block ap_a_03_f;

end architecture test;