library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ap_a_04 is
end entity ap_a_04;


architecture test of ap_a_04 is

begin

  ap_a_04_a : block

    signal clk : bit;
    signal data_in, reg_out : bit;

  begin

    -- code from book

    simple_reg : process ( clk )
    begin
      if clk'event and clk = '1' then
        reg_out <= data_in;
      end if;
    end process simple_reg;

    -- end code from book

  end block ap_a_04_a;

  --

  ap_a_04_b : block

    signal clk, rst_n, load : std_logic;
    signal load_data, q : unsigned(7 downto 0);

  begin

    -- code from book

    count_byte : process ( clk, rst_n, load, load_data )
      variable count : unsigned(7 downto 0);
    begin
      if std_match(rst_n, '0') then
        count := "00000000";
        q <= count;
      elsif std_match(load, '1') then
        count := load_data;
        q <= count;
      elsif rising_edge(clk) then
        count := count + 1;
        q <= count;
      end if;
    end process count_byte;

    -- end code from book

  end block ap_a_04_b;

  --

  ap_a_04_c : block

    signal clk, load, serial_data_in : bit;
    signal load_data_in, q : bit_vector(7 downto 0);

  begin

    -- code from book

    shift_reg : process
      variable stored_value : bit_vector(7 downto 0);
    begin
      wait until clk = '1';
      if load = '1' then
        stored_value := load_data_in;
        q <= stored_value;
      else
        stored_value := stored_value(6 downto 0) & serial_data_in;
        q <= stored_value;
      end if;
    end process shift_reg;

    -- end code from book

  end block ap_a_04_c;

  --

  ap_a_04_d : block

    signal enable, d, q : bit;

  begin

    -- code from book

    latch : process ( enable, d )
    begin
      if enable = '1' then
        q <= d;
      end if;
    end process latch;

    -- end code from book

  end block ap_a_04_d;

  --

  ap_a_04_e : block

    signal enable, reset, d, q : bit;

  begin

    -- code from book

    latch_with_reset : process ( enable, reset, d )
      variable stored_value : bit;
    begin
      if reset = '1' then
        stored_value := '0';
      elsif enable = '1' then
        stored_value := d;
      end if;
      q <= stored_value;
    end process latch_with_reset;

    -- end code from book

  end block ap_a_04_e;

  --

  ap_a_04_f : block

    signal count_en : bit;
    signal q : natural range 0 to 15;

  begin

    -- code from book

    counter : process ( count_en )
      variable count : natural range 0 to 15;
    begin
      q <= (q + 1) mod 16;
    end process counter;

    -- end code from book

  end block ap_a_04_f;

end architecture test;