entity state_machine is
  port ( clk, reset : in bit;
         in1, in2 : in bit;
         out1, out2 : out bit );
end entity state_machine;

-- code from book

architecture rtl of state_machine is
  type state is (ready, ack, err);
  signal current_state, next_state : state;
begin

  next_state_and_output : process ( current_state, in1, in2 )
  begin
    case current_state is
      when ready =>
        out1 <= '0';
        if in1 = '1' then
          out2 <= '1';
          next_state <= ack;
        else
          out2 <= '0';
          next_state <= ready;
        end if;
      when ack =>
        out1 <= '0';
        if in2 = '1' then
          out2 <= '0';
          next_state <= ready;
        else
          out2 <= '0';
          next_state <= err;
        end if;
      when err =>
        out1 <= '1';
        out2 <= '0';
        next_state <= err;
    end case;
  end process next_state_and_output;

  state_reg : process ( clk, reset )
  begin
    if reset = '1' then
      current_state <= ready;
    elsif clk'event and clk = '1' then
      current_state <= next_state;
    end if;
  end process state_reg;

end rtl;

-- end code from book


entity fg_a_01 is
end entity fg_a_01;


architecture test of fg_a_01 is

  signal clk, reset : bit;
  signal in1, in2 : bit;
  signal out1, out2 : bit;      

begin

  clk_gen : process is
  begin
    clk <= '1', '0' after 5 ns;
    wait for 10 ns;
  end process clk_gen;

  reset <= '1', '0' after 35 ns;

  bit_vector'(in1, in2) <= "11" after 5 ns,        -- reset active
                           "00" after 15 ns,       -- reset active
                           "00" after 25 ns,       -- reset active
                           "00" after 35 ns,       --> ready/0/0
                           "00" after 45 ns,       --> ready/0/0
                           "01" after 55 ns,       --> ready/0/0
                           "10" after 65 ns,       --> ack/0/1
                           "01" after 75 ns,       --> ready/0/0
                           "11" after 85 ns,       --> ack/0/1
                           "11" after 95 ns,       --> ready/0/0
                           "10" after 105 ns,      --> ack/0/1
                           "10" after 115 ns,      --> error/1/0
                           "11" after 125 ns,      --> error/1/0
                           "00" after 135 ns;      --> error/1/0  

end architecture test;