library ieee;  use ieee.std_logic_1164.all;
library cell_lib;

entity interlock_control is
end entity interlock_control;


-- code from book

architecture detailed_timing of interlock_control is

  component nor_gate is
    generic ( input_width : positive );
    port ( input : in std_logic_vector(0 to input_width - 1);
           output : out std_logic );
  end component nor_gate;

  for ex_interlock_gate : nor_gate
    use entity cell_lib.nor_gate(primitive)
    generic map ( width => input_width,
                  Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates

  -- . . .

  -- not in book
  signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
  -- end not in book

begin

  ex_interlock_gate : component nor_gate
    generic map ( input_width => 2 )
    port map ( input(0) => reg_access_hazard,
               input(1) => load_hazard,
               output => stall_ex_n);

  -- . . .

  -- not in book

  reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;

  load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
                 '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
                 '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
                 '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;

  -- end not in book

end architecture detailed_timing;

-- end code from book