fg_13_01.vhd	entity edge_triggered_Dff
		architecture basic of edge_triggered_Dff
		architecture hi_fanout of edge_triggered_Dff
		entity reg4
		architecture struct of reg4
		configuration fg_13_01 of reg4

fg_13_02.vhd	package serial_interface_defs

fg_13_03.vhd	entity serial_interface
		architecture test of serial_interface

fg_13_04.vhd	entity microcontroller
		architecture structure of microcontroller

tb_13_01.vhd	entity edge_triggered_Dff
		architecture basic of edge_triggered_Dff
		architecture hi_fanout of edge_triggered_Dff

fg_13_05.vhd	configuration reg4_gate_level of reg4
		entity fg_13_05
		architecture test of fg_13_05
		configuration fg_13_05_test of fg_13_05

fg_13_06.vhd	package counter_types
		entity add_1
		architecture boolean_eqn of add_1
		entity buf4
		architecture basic of buf4
		entity counter
		architecture registered of counter

fg_13_07.vhd	configuration counter_down_to_gate_level of counter
		entity fg_13_07
		architecture test of fg_13_07

fg_13_08.vhd	configuration full of counter
		entity fg_13_08
		architecture test of fg_13_08

fg_13_09.vhd	entity alarm_clock
		architecture top_level of alarm_clock

fg_13_10.vhd	entity reg
		architecture gate_level of reg

fg_13_11.vhd	entity controller
		architecture structural of controller

fg_13_12.vhd	configuration controller_with_timing of circuit

fg_13_13.vhd	entity computer_system
		architecture structure of computer_system

fg_13_14.vhd	entity decoder_3_to_8
		architecture basic of decoder_3_to_8

fg_13_15.vhd	configuration computer_structure of computer_system

fg_13_17.vhd	entity single_board_computer
		architecture structural of single_board_computer

tb_13_02.vhd	entity XYZ3000_cpu
		architecture full_function of XYZ3000_cpu

fg_13_18.vhd	entity memory_array
		architecture behavioral of memory_array
		configuration intermediate of single_board_computer

tb_13_03.vhd	entity nand3
		architecture behavioral of nand3

fg_13_19.vhd	entity logic_block
		architecture ideal of logic_block

fg_13_21.vhd	entity reg
		architecture gate_level of reg

fg_13_20.vhd	entity control_section
		architecture structural of control_section

fg_13_22.vhd	configuration controller_with_timing of control_section

tb_13_04.vhd	entity nor_gate
		architecture primitive of nor_gate

fg_13_23.vhd	entity interlock_control
		architecture detailed_timing of interlock_control

fg_13_24.vhd	configuration interlock_control_with_estimates of interlock_control
		configuration interlock_control_with_actual of interlock_control

tb_13_05.vhd	entity nand3
		architecture basic of nand3

fg_13_25.vhd	entity misc_logic
		architecture gate_level of misc_logic

fg_13_26.vhd	configuration misc_logic_reconfigured of misc_logic

ch_13_01.vhd	entity ch_13_01
		architecture test of ch_13_01
		entity nand2
		configuration ch_13_01_test of ch_13_01