-- analyze into resource library cell_lib


library ieee;  use ieee.std_logic_1164.all;

entity nor_gate is
  generic ( width : positive;
            Tpd01, Tpd10 : delay_length );
  port ( input : in std_logic_vector(0 to width - 1);
         output : out std_logic );
end entity nor_gate;


architecture primitive of nor_gate is

  function max ( a, b : delay_length ) return delay_length is
  begin
    if a > b then
      return a;
    else
      return b;
    end if;
  end function max;

begin

  reducer : process (input) is
    variable result : std_logic;
  begin
    result := '0';
    for index in input'range loop
      result := result or input(index);
    end loop;
    if not result = '1' then
      output <= not result after Tpd01;
    elsif not result = '0' then
      output <= not result after Tpd10;
    else
      output <= not result after max(Tpd01, Tpd10);
    end if;
  end process reducer;

end architecture primitive;