-- to be analyzed into resource library cell_lib


library ieee;  use ieee.std_logic_1164.all;

entity D_flipflop is
  port ( clk : in std_logic;  d : in std_logic;
         q : out std_logic );
end entity D_flipflop;


architecture synthesized of D_flipflop is
begin
  q <= d when not clk'stable and (To_X01(clk) = '1') and 
                                 (To_X01(clk'last_value) = '0');
end architecture synthesized;


library ieee;  use ieee.std_logic_1164.all;

entity tristate_buffer is
  port ( a : in std_logic;
         en : in std_logic;
         y : out std_logic );
end entity tristate_buffer;


architecture synthesized of tristate_buffer is
begin
  y <= 'X' when is_X(en) else
        a  when To_X01(en) = '1' else
       'Z';
end architecture synthesized;