-- to be analyzed into resource library cell_lib


library ieee;  use ieee.std_logic_1164.all;

entity ms_flipflop is
  port ( phi1, phi2 : in std_logic;
         d : in std_logic;
         q : out std_logic );
end entity ms_flipflop;


architecture normal_drive of ms_flipflop is
  signal master_d : std_logic;
begin
  master_d <= d when phi1 = '1';
  q <= master_d when phi2 = '1';
end architecture normal_drive;


architecture high_drive of ms_flipflop is
  signal master_d : std_logic;
begin
  master_d <= d when phi1 = '1';
  q <= master_d when phi2 = '1';
end architecture high_drive;