architecture behavior of clock_gen is
begin

  reset_driver : 
    reset <= '1', '0' after 3.5 * Tclk;

  clock_driver : process is
  begin
    clk <= '0';
    wait for Tclk;
    loop
      clk <= '1', '0' after Tclk / 2;
      wait for Tclk;
    end loop;
  end process clock_driver;

end architecture behavior;