library ieee;  use ieee.std_logic_1164.all, ieee.numeric_bit.all;

use work.dlx_instr.all, work.alu_types.all;

architecture rtl of dlx is

  component alu is
    port ( s1 : in dlx_word;
           s2 : in dlx_word;
           result : out dlx_word;
           func : in alu_func;
           zero, negative, overflow : out bit );
  end component alu;

  component reg_file is
    port ( a1 : in dlx_reg_addr;
           q1 : out dlx_word;
           a2 : in dlx_reg_addr;
           q2 : out dlx_word;
           a3 : in dlx_reg_addr;
           d3 : in dlx_word;
           write_en : in bit );
  end component reg_file;

  component ir_extender is
    port ( d : in dlx_word;
           q : out dlx_bus_word;
           immed_size_26 : in bit;
           immed_unsigned : in bit;
           immed_en : in bit );
  end component ir_extender;

  component reg is
    port ( d : in dlx_word;
           q : out dlx_word;
           clk, enable : in bit );
  end component reg;

  component reg_multiple_out is
    generic ( num_outputs : positive );
    port ( d : in dlx_word;
           q : out dlx_bus_word_array(1 to num_outputs);
           clk, enable : in bit;
           out_en : in bit_vector(1 to num_outputs) );
  end component reg_multiple_out;

  component reg_multiple_plus_one_out is
    generic ( num_outputs : positive );
    port ( d : in dlx_word;
           q0 : out dlx_word;
           q : out dlx_bus_word_array(1 to num_outputs);
           clk, enable : in bit;
           out_en : in bit_vector(1 to num_outputs) );
  end component reg_multiple_plus_one_out;

  component reg_multiple_plus_one_out_reset is
    generic ( num_outputs : positive );
    port ( d : in dlx_word;
           q0 : out dlx_word;
           q : out dlx_bus_word_array(1 to num_outputs);
           clk, enable : in bit;
           out_en : in bit_vector(1 to num_outputs);
           reset : in bit );
  end component reg_multiple_plus_one_out_reset;

  component mux2 is
    port ( i0, i1 : in dlx_word;
           y : out dlx_word;
           sel : in bit);
  end component mux2;

  component controller is
    port ( clk : in bit;
           reset : in bit;
           halt : out bit;
           width : out dlx_mem_width;
           write_enable : out bit;
           mem_enable : out bit;
           ifetch : out bit;
           ready : in bit;
           alu_function : out alu_func;
           alu_zero, alu_negative, alu_overflow : in bit;
           reg_s1_addr, reg_s2_addr, reg_dest_addr : out dlx_reg_addr;
           reg_write : out bit;
           c_enable : out bit;
           a_enable, a_out_en : out bit;
           b_enable, b_out_en : out bit;
           temp_enable, temp_out_en1, temp_out_en2 : out bit;
           pc_enable, pc_out_en1, pc_out_en2 : out bit;
           mar_enable, mar_out_en1, mar_out_en2 : out bit;
           mem_addr_mux_sel : out bit;
           mdr_enable, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out bit;
           mdr_mux_sel : out bit;
           ir_enable : out bit;
           ir_immed1_size_26, ir_immed2_size_26 : out bit;
           ir_immed1_unsigned, ir_immed2_unsigned : out bit;
           ir_immed1_en, ir_immed2_en : out bit;
           current_instruction : in dlx_word;
           mem_addr : unsigned(1 downto 0);
           const2 : out dlx_bus_word );
  end component controller;


  signal s1_bus, s2_bus : dlx_bus_word;
  signal dest_bus : dlx_word;
  signal s1_in, s2_in, d_in : dlx_word;
  signal alu_in1, alu_in2 : dlx_word;
  signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
  signal mdr_in : dlx_word;
  signal current_instruction : dlx_word;
  signal pc_to_mem : dlx_address;
  signal mar_to_mem : dlx_address;

  signal alu_function : alu_func;
  signal alu_zero, alu_negative, alu_overflow : bit;
  signal reg_s1_addr, reg_s2_addr, reg_dest_addr : dlx_reg_addr;
  signal reg_write : bit;
  signal a_out_en, a_enable : bit;
  signal b_out_en, b_enable : bit;
  signal c_enable : bit;
  signal temp_out_en1, temp_out_en2, temp_enable : bit;
  signal pc_out_en1, pc_out_en2, pc_enable : bit;
  signal mar_out_en1, mar_out_en2, mar_enable : bit;
  signal mem_addr_mux_sel : bit;
  signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_enable : bit;
  signal mdr_mux_sel : bit;
  signal ir_enable : bit;
  signal ir_immed1_size_26, ir_immed2_size_26 : bit;
  signal ir_immed1_unsigned, ir_immed2_unsigned : bit;
  signal ir_immed1_en, ir_immed2_en : bit;

begin

  s1_in <= dlx_word(To_bitvector(s1_bus));
  s2_in <= dlx_word(To_bitvector(s2_bus));
  d_in <= dlx_word(To_bitvector(d));

  the_alu : component alu
    port map ( s1 => s1_in, s2 => s2_in, result => dest_bus,
               func => alu_function,
               zero => alu_zero, negative => alu_negative, overflow => alu_overflow );

  the_reg_file : component reg_file
    port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
               a2 => reg_s2_addr, q2 => reg_file_out2,
               a3 => reg_dest_addr, d3 => reg_file_in,
               write_en => reg_write );

  c_reg : component reg
    port map ( d => dest_bus, q => reg_file_in,
               clk => clk, enable => c_enable );

  a_reg : component reg_multiple_out
    generic map ( num_outputs => 1 )
    port map ( d => reg_file_out1, q(1) => s1_bus,
               clk => clk, enable => a_enable, out_en(1) => a_out_en );

  b_reg : component reg_multiple_out
    generic map ( num_outputs => 1 )
    port map ( d => reg_file_out2, q(1) => s2_bus,
               clk => clk, enable => b_enable, out_en(1) => b_out_en );

  temp_reg : component reg_multiple_out
    generic map ( num_outputs => 2 )
    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
               clk => clk, enable => temp_enable,
               out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );

  pc_reg : component reg_multiple_plus_one_out_reset
    generic map ( num_outputs => 2 )
    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
               clk => clk, enable => pc_enable,
               out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
               reset => reset );

  mar_reg : component reg_multiple_plus_one_out
    generic map ( num_outputs => 2 )
    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
               clk => clk, enable => mar_enable,
               out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );

  mem_addr_mux : component mux2
    port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
               sel => mem_addr_mux_sel );

  mdr_reg : component reg_multiple_out
    generic map ( num_outputs => 3 )
    port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
               clk => clk, enable => mdr_enable,
               out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
               out_en(3) => mdr_out_en3 );

  mdr_mux : component mux2
    port map ( i0 => dest_bus, i1 => d_in, y => mdr_in,
               sel => mdr_mux_sel );

  instr_reg : component reg
    port map ( d => d_in, q => current_instruction,
               clk => clk, enable => ir_enable );

  ir_extender1 : component ir_extender
    port map ( d => current_instruction, q => s1_bus,
               immed_size_26 => ir_immed1_size_26,
               immed_unsigned => ir_immed1_unsigned,
               immed_en => ir_immed1_en );

  ir_extender2 : component ir_extender
    port map ( d => current_instruction, q => s2_bus,
               immed_size_26 => ir_immed2_size_26,
               immed_unsigned => ir_immed2_unsigned,
               immed_en => ir_immed2_en );

  the_controller : component controller
    port map ( clk => clk, reset => reset, halt => halt, 
               width => width, write_enable => write_enable,
               mem_enable => mem_enable,
               ifetch => ifetch, ready => ready, 
               alu_function => alu_function,
               alu_zero => alu_zero, alu_negative => alu_negative,
               alu_overflow => alu_overflow,
               reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
               reg_dest_addr => reg_dest_addr, reg_write => reg_write, 
               c_enable => c_enable,
               a_enable => a_enable, a_out_en => a_out_en,
               b_enable => b_enable, b_out_en =>  b_out_en, 
               temp_enable => temp_enable,
               temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2, 
               pc_enable => pc_enable,
               pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2, 
               mem_addr_mux_sel => mem_addr_mux_sel,
               mar_enable => mar_enable,
               mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
               mdr_mux_sel => mdr_mux_sel, mdr_enable => mdr_enable,
               mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2, 
               mdr_out_en3 => mdr_out_en3, 
               ir_enable => ir_enable,
               ir_immed1_size_26 => ir_immed1_size_26,
               ir_immed2_size_26 => ir_immed2_size_26,
               ir_immed1_unsigned => ir_immed1_unsigned,
               ir_immed2_unsigned => ir_immed2_unsigned,
               ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,  
               current_instruction => current_instruction,
               mem_addr => mar_to_mem(1 downto 0),
               const2 => s2_bus );

end architecture rtl;