architecture bench of dlx_test is

  use work.dlx_types.all;

  component clock_gen is
    port ( clk : out bit;
           reset : out bit );
  end component clock_gen;

  component memory is
    port ( clk : in bit;
           a : in dlx_address;
           d : inout dlx_bus_word;
           width : in dlx_mem_width;
           write_enable : in bit;
           burst : in bit := '0';
           mem_enable : in bit;
           ready : out bit );
  end component memory;

  component dlx is
    port ( clk : in bit;
           reset : in bit;
           halt : out bit;
           a : out dlx_address;
           d : inout dlx_bus_word;
           width : out dlx_mem_width;
           write_enable : out bit;
           ifetch : out bit;
           mem_enable : out bit;
           ready : in bit );
  end component dlx;

  signal clk, reset : bit;
  signal a : dlx_address;
  signal d : dlx_bus_word;
  signal halt : bit;
  signal width : dlx_mem_width;
  signal write_enable, mem_enable, ifetch, ready : bit;

begin

  cg : component clock_gen
    port map ( clk => clk, reset => reset );

  mem : component memory
    port map ( clk => clk,
               a => a, d => d,
               width => width, write_enable => write_enable, burst => open,
               mem_enable => mem_enable, ready => ready );

  proc : component dlx
    port map ( clk => clk, reset => reset, halt => halt,
               a => a, d => d,
               width => width, write_enable => write_enable, ifetch => ifetch,
               mem_enable => mem_enable, ready => ready );

end architecture bench;