dlx_types.vhdl
	Package specification for types used in dlx model

dlx_instr.vhdl
	Package specification for DLX instructions
dlx_instr-body.vhdl
	Package body for DLX instructions

dlx.vhdl
	Entity specification for DLX processor

dlx-behavior.vhdl
	Behavioral architecture for DLX processor

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clock_gen.vhdl
	Entity declaration for clock generator
clock_gen-behavior.vhdl
	Behavioral architecture body for clock generator

memory.vhdl
	Entity declaration for memory model
memory-preloaded.vhdl
	Behavioral architecture for memory model, including a
	"preloaded" (initialized) memory array
memory-file_loaded.vhdl
	Behavioral architecture for memory model that loads the
	memory array from a file

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dlx_test.vhdl
	Entity declaration for test bench for DLX
dlx_test-bench.vhdl
	Architecture for test bench for DLX,
	including clock generator and memory

dlx_test_behavior.vhdl
	Configuration of test bench for DLX, using architecture behavior

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alu_types.vhdl
	Package defining types for ALU.
alu.vhdl
	Entity declaration for ALU.
alu-behavior.vhdl
	Behavioral architecture of ALU.

ir_extender.vhdl
	Entity declaration for instruction register immediate extender.
ir_extender-behavior.vhdl
	Behavioral architecture of instruction register immediate extender.

reg.vhdl
	Entity declaration for simple register.
reg-behavior.vhdl
	Behavioral architecture of simple register.

mux2.vhdl
	Entity declaration for two-input multiplexor.
mux2-behavior.vhdl
	Behavioral architecture of two-input multiplexor.

reg_multiple_out.vhdl
	Entity declaration for register with multiple tri-state outputs.
reg_multiple_out-behavior.vhdl
	Behavioral architecture of register with multiple tri-state outputs.

reg_multiple_plus_one_out.vhdl
	Entity declaration for register with multiple tri-state outputs
	plus one ordinary output.
reg_multiple_plus_one_out-behavior.vhdl
	Behavioral architecture of register with multiple tri-state outputs
	plus one ordinary output.

reg_multiple_plus_one_out_reset.vhdl
	Entity declaration for register with multiple tri-state outputs
	plus one ordinary output, and asynchronous reset.
reg_multiple_plus_one_out_reset-behavior.vhdl
	Behavioral architecture of register with multiple tri-state outputs
	plus one ordinary output, and asynchronous reset.

reg_file.vhdl
	Entity declaration for register file.
reg_file-behavior.vhdl
	Behavioral architecture of register file.

controller.vhdl
	Entity declaration for DLX control section.
controller-behavior.vhdl
	Behavioral architecture of DLX control section.

dlx-rtl.vhdl
	Register transfer level architecture of DLX processor.

dlx_rtl.vhdl
	Configuration declaration for DLX entity, selecting the
	register transfer level architecture.

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dlx_test_rtl.vhdl
	Configuration of DLX test bench using register transfer level
	configuration of the DLX processor.

dlx_test-verifier.vhdl
	Architecture for test bench for DLX, including clock generator
	and memory, and two instances of the CPU.  The outputs of the
	CPU instances are compared against each other.

dlx_test_verifier.vhdl
	Configuration of DLX verifier test bench using behavioural
	architecture for one CPU and register transfer level configuration
	for the other CPU.