library ieee;  use ieee.numeric_bit.all;

architecture behavior of reg_file is
begin

  reg: process ( a1, a2, a3, d3, write_en ) is

    constant all_zeros : dlx_word := X"0000_0000";

    subtype register_array is dlx_word_array(1 to 31);

    variable register_file : register_array;
    variable reg_index1, reg_index2, reg_index3 : reg_index;

  begin
    -- do write first if enabled
    if write_en = '1' then
      reg_index3 := to_integer(a3);
      if reg_index3 /= 0 then
        register_file(reg_index3) := d3;
      end if;
    end if;

    -- read port 1
    reg_index1 := to_integer(a1);
    if reg_index1 /= 0 then
      q1 <= register_file(reg_index1) after Tac;
    else
      q1 <= all_zeros after Tac;
    end if;

    -- read port 2
    reg_index2 := to_integer(a2);
    if reg_index2 /= 0 then
      q2 <= register_file(reg_index2) after Tac;
    else
      q2 <= all_zeros after Tac;
    end if;
  end process reg;

end architecture behavior;