use work.dlx_types.all, work.dlx_instr.all;

entity reg_file is
  generic ( Tac : delay_length );
  port ( a1 : in dlx_reg_addr;
         q1 : out dlx_word;
         a2 : in dlx_reg_addr;
         q2 : out dlx_word;
         a3 : in dlx_reg_addr;
         d3 : in dlx_word;
         write_en : in bit);
end entity reg_file;