library ieee;  use ieee.std_logic_1164.all;

architecture behavior of reg_multiple_plus_one_out is

  signal stored_value : dlx_word;
  
begin

  reg: process ( clk ) is
  begin
    if clk = '1' and clk'event then
      if enable = '1' then
        stored_value <= d;
      end if;
    end if;
  end process reg;

  q0 <= stored_value after Tpd;

  tristate_out : for index in out_en'range generate
      
    q(index) <= to_X01(bit_vector(stored_value)) after Tpd
                  when out_en(index) = '1' else
                disabled_dlx_word after Tpd;

  end generate;

end architecture behavior;