use work.dlx_types.all;

entity reg_multiple_plus_one_out_reset is
  generic ( num_outputs : positive;
            Tpd : delay_length );
  port ( d : in dlx_word;
         q0 : out dlx_word;
         q : out dlx_bus_word_array(1 to num_outputs);
         clk, enable : in bit;
         out_en : in bit_vector(1 to num_outputs);
         reset : in bit );
end entity reg_multiple_plus_one_out_reset;