fg_16_01.vhd	entity computer_system
		architecture top_level of computer_system

fg_16_02.vhd	entity processor
		architecture rtl of processor

fg_16_04.vhd	package fg_16_04
		package body fg_16_04

fg_16_05.vhd	entity tri_state_reg
		architecture behavioral of tri_state_reg
		entity fg_16_05
		architecture test of fg_16_05

fg_16_06.vhd	entity data_logger
		architecture high_level of data_logger

fg_16_07.vhd	entity fg_16_07
		architecture test of fg_16_07

fg_16_08.vhd	entity processor_node
		architecture dataflow of processor_node

fg_16_09.vhd	entity latch
		architecture behavioral of latch

fg_16_10.vhd	entity computer_system
		architecture abstract of computer_system

fg_16_12.vhd	entity counter

fg_16_13.vhd	architecture detailed_timing of counter
		entity fg_16_13
		architecture test of fg_16_13

fg_16_14.vhd	entity example_entity
		architecture contrived of example_entity

fg_16_15.vhd	entity circuit
		architecture with_pad_delays of circuit

fg_16_16.vhd	entity real_subcircuit
		architecture basic of real_subcircuit
		configuration full of circuit
		entity fg_16_16
		architecture test of fg_16_16

ch_16_01.vhd	entity ch_16_01
		architecture test of ch_16_01

ch_16_02.vhd	entity ch_16_02
		architecture test of ch_16_02

ch_16_03.vhd	entity ch_16_03
		architecture test of ch_16_03

ch_16_04.vhd	entity ch_16_04
		architecture test of ch_16_04

ch_16_05.vhd	entity ch_16_05
		architecture test of ch_16_05

ch_16_06.vhd	entity ch_16_06
		architecture test of ch_16_06