-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : e_Integ.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/11/09
-- Last update: 2003-05-20
-------------------------------------------------------------------------------
-- Description: Integrator Block with electrical connections. 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/11/09  1.0         Mentor Graphics     Created 
-- 2003/03/26  1.1         Mentor Graphics     Added init to equation
-- 2003/04/15  1.2         Mentor Graphics     Add z-domain architecture      
-------------------------------------------------------------------------------
library IEEE;
use IEEE.electrical_systems.all;
use ieee.math_real.all;

entity e_Integ is
  generic (
    k     : real := 1.0;    -- Gain
    init  : real := 0.0;    -- Initial value of output
    Fsmp  : real := 10.0e3  -- For Z-dmn only: Sample frequency (in Hz)
    );
  port (terminal input  : electrical;
        terminal output : electrical);
end entity e_Integ;
-------------------------------------------------------------------------------
-- Transfer Function:
--
--          k
-- H(s) = ----- + init
--          s 
-------------------------------------------------------------------------------

-- S Domain Implementation
architecture s_dmn of e_Integ is
  quantity vin across input to electrical_ref;
  quantity vout across iout through output to electrical_ref;
begin
  if domain = quiescent_domain use
    vout == init;
else
  vout   == k*vin'integ + init;
end use;
end architecture s_dmn;

-- Z Domain Implementation (via bilinear transform, no pre-warping)
architecture z_dmn of e_Integ is
  quantity vin across input to electrical_ref;
  quantity vout across iout through output to electrical_ref;
  constant Tsmp   : real := 1.0/Fsmp;  -- Sample period
  constant numz_0 : real := Tsmp;      -- z0 numerator coefficient 
  constant numz_1 : real := Tsmp;      -- z-1 numerator coefficient 
  constant denz_0 : real := 2.0;       -- z0 denominator coefficient 
  constant denz_1 : real := -2.0;      -- z-1 denominator coefficient 
  constant num    : real_vector := (numz_0, numz_1);
  constant den    : real_vector := (denz_0, denz_1);
begin  -- ztf
  vout == k*vin'Ztf(num, den, Tsmp) + init;
end z_dmn;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------