------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : e_Limit.vhd -- Author : Mentor Graphics -- Created : 2003/03/26 -- Last update: 2003-05-20 ------------------------------------------------------------------------------- -- Description: Limiter with electrical connections. Limits have a small slope -- whose default value is 1.0e-4. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/03/26 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.electrical_systems.all; use ieee.math_real.all; entity e_Limit is generic ( limit_high : real := 5.0; -- upper limit limit_low : real := -5.0); -- lower limit port ( terminal input : electrical; terminal output : electrical); end entity e_Limit; architecture simple of e_Limit is constant slope : real := 1.0e-4; quantity vin across input to electrical_ref; quantity vout across iout through output to electrical_ref; begin if vin'above(limit_high) use -- High limit exceeded, limit input signal vout == limit_high + slope*(vin - limit_high); elsif not vin'above(limit_low) use -- Low limit exceeded, limit input signal vout == limit_low + slope*(vin - limit_low); else -- No limit exceeded, pass input signal vout == vin; end use; break on vin'above(limit_high), vin'above(limit_low); end architecture simple; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -------------------------------------------------------------------------------