-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
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-- File       : q_PWL_tf.vhd
-- Author     : Mentor Graphics
-- Created    : 2003/03/26
-- Last update: 2003-05-30
-------------------------------------------------------------------------------
-- Description: Piece-wise Linear function block with real quantity
-- connections.  This non-linear (PWL) block model is used to create a
-- user-defined transfer function. The PWL lookup points are specified as
-- a collection of real vectors.
-- Ex: If you set in_data to (0.0, 1.0, 5.0), and set out_data to (0.0, 10.0,
-- 50.0), any inputs between 0.0 and 1.0 will produce a relative output
-- between 0.0 and 10.0, etc. 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003/03/26  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

library IEEE;
use IEEE.MATH_REAL.all;
-- The pwl_functions package contains general purpose PWL functions and is
-- compiled into the MGC_AMS library.
-- Source file: mgc_ams_pwl_functions.vhd 
library mgc_ams;                
use mgc_ams.pwl_functions.all; 

entity q_PWL_tf is
  generic (in_data  :  real_vector;
           out_data :  real_vector);  -- PWL data (out vs. in)
  port (quantity    input  : in  real;
        quantity output : out real);
end entity q_PWL_tf;

architecture behavioral of q_PWL_tf is
  -- Call function to check for monotonically increasing vector
  constant mono_data : boolean := monotonically_increasing(in_data);

begin
  -- Check for monotonically increasing X vector (in_data)
  assert mono_data
	report "in_data must be monotonically increasing"
	severity error;
  
  output == pwl_dim1_extrap(input, in_data, out_data);  -- Call PWL function
end architecture behavioral;

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-- Copyright (c) 2003 Mentor Graphics Corporation
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