-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
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-- notice that this model has been modified and the date of modification; and 
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-- conspicuous notice that this model is available from Mentor Graphics in its
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-------------------------------------------------------------------------------
-- File       : JKFF.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-03-28
-- Last update: 2003-04-22
-------------------------------------------------------------------------------
-- Description: JK flip flop with preset and clear
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-03-28  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity JKFF is
  generic (
    delay : time := 0 ns);              -- Delay time

  port (
    j, k, clk : in  std_logic;
    q         : inout std_logic := '0';   -- initially in "cleared" state
    qn        : out std_logic   := '1';
    p         : in  std_logic   := '1';   -- preset (negative logic)
    c         : in  std_logic   := '0');  -- clear (negative logic)

end entity JKFF;

architecture ideal of JKFF is
begin
  process (clk, p, c) is 
  begin
    if c = '0' then q <= '0' after delay;    -- clear output to '0'
    elsif p = '0' then q <= '1' after delay; -- preset output to '1'
    elsif clk = '1' and clk'event then        -- positive edge triggered
      q <= (j and not q) or (not k and q) after delay;
    end if;
  end process;
  
  qn <= not q;

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------