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-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-- File       : clock_en.vhd
-- Author     : Mentor Graphics
-- Created    : 2003/04/21
-- Last update: 2003/04/23
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-- Description: Digital clock with 50% duty cycle and enable
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-- Revisions  :
-- Date        Version     Author              Description
-- 2003/04/21  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity clock_en is
  generic (
    period  :     time);  -- Clock period
  port (
    enable  : in  std_logic;
    clk_out : out std_logic);
end entity clock_en;

architecture ideal of clock_en is
begin
  CreateClock : process
  begin
    if enable = '1' then
      clk_out <= '0';
      wait for period/2;
      clk_out <= '1';
      wait for period/2;
    else
      clk_out <= '0';
      wait for period/2;
    end if;
  end process CreateClock;
end architecture ideal;

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-- Copyright (c) 2001 Mentor Graphics Corporation
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