-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
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-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : d_bus_cmp.vhd
-- Author     : Mentor Graphics
-- Created    : 2003/04/21
-- Last update: 2003/04/23
-------------------------------------------------------------------------------
-- Description: Digital bus comparator
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003/04/21  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------
-- N-bit digital comparator model
-- '1' on the latch_in1 or latch_in2 ports causes bus data on in1 or in2 to be
--   latched and stored in its respective internal register
-- '1' on the cmp ports initiates a comparison between latched data, and if equal,
--   a '1' is sent to the output port, eq.
library IEEE;
use IEEE.std_logic_1164.all;

entity d_bus_cmp is
  generic (Nbits :     integer   := 12);  -- User-defined bus width
  port
    (
      eq         : out std_logic := '0';
      in1        : in  std_logic_vector (0 to Nbits-1);  -- Input bus #1
      in2        : in  std_logic_vector (0 to Nbits-1);  -- Input bus #2
      latch_in1  : in  std_logic := '0';  -- in1 latch command
      latch_in2  : in  std_logic := '0';  -- in2 latch command
      cmp        : in  std_logic := '0'  -- Compare control
      );
end entity d_bus_cmp;

architecture simple of d_bus_cmp is
begin
  compare : process (latch_in1, latch_in2, cmp)  -- Sensitivity list
    variable in1_hold : std_logic_vector (0 to (Nbits-1));
    variable in2_hold : std_logic_vector (0 to (Nbits-1));
  begin
    if latch_in1'event and latch_in1 = '1' then  -- in1 data is latched and stored
      in1_hold := in1;
    end if;
    if latch_in2'event and latch_in2 = '1' then  -- in2 data is latched and stored
      in2_hold := in2;
    end if;
    if cmp'event and cmp = '1' then
      if in1_hold = in2_hold then       -- compare latched values
        eq    <= '1';                   -- if equal, set output to '1'
      else eq <= '0';                   -- if unequal, set output to '0'
      end if;
    end if;
  end process;
end architecture simple;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------