-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
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-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
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-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : dig_pulse.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/06/16
-- Last update: 2002-07-25
-------------------------------------------------------------------------------
-- Description: Digital Pulse Source with Period and Duty Cycle generics
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/06/16  1.0         Mentor Graphics     Created
-- 2002/05/24  1.1         Mentor Graphics     Added "duty" generic
-- 2002/07/25  1.2         Mentor Graphics     Fixed initial_delay operation
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity dig_pulse is
  generic (initial_delay : delay_length := 1 ns;     -- Delay Time [Sec]
           duty          : real := 0.5;              -- Duty Cycle
           period        : delay_length := 20 ns);   -- Period [Sec]

  port (out_state : out std_logic);

end entity dig_pulse;


architecture ideal of dig_pulse is

  signal   out_signal : std_logic;
  constant on_time    : delay_length := duty * period;
  constant off_time   : delay_length := period - on_time;

begin
-- Check for Duty Cycle
  assert duty > 0.0 and duty < 1.0
    report "Duty Cycle must be between 0 and 1"
    severity ERROR;
  
-- purpose: Creates events on signal "out_signal"
-- type   : combinational
-- inputs : 
-- outputs: out_signal  
  CreateEvent : process
  begin
      out_signal <= '0';
      wait for initial_delay;
	loop
      out_signal <= '1';
      wait for on_time;
      out_signal <= '0';
      wait for off_time;
    end loop;
  end process CreateEvent;

  out_state <= out_signal;

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------