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-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- notice that this model has been modified and the date of modification; and 
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-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-- File       : mux4.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-03-28
-- Last update: 2003-03-28
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-- Description: 4 to 1 multiplexer with enable 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-03-28  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity mux4 is
  port ( sel            : in  std_logic_vector;  -- 2-bit bus select signal
         en             : in  std_logic;         -- enable pin
         d0, d1, d2, d3 : in  std_logic;         -- input signals    
         output         : out std_logic );
end entity mux4;

architecture ideal of mux4 is
begin
  
  output <= d0 when sel = b"00" and en = '1' else  -- set output to appropriate
            d1 when sel = b"01" and en = '1' else  -- input based on select 
            d2 when sel = b"10" and en = '1' else  -- signal bit values
            d3 when sel = b"11" and en = '1' else 
            'Z';                                   -- output is undefined
  
end architecture ideal;

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-- Copyright (c) 2003 Mentor Graphics Corporation
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