-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
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-- File       : p2s_shift_reg.vhd
-- Author     : Mentor Graphics
-- Created    : 2003/04/21
-- Last update: 2003/04/23
-------------------------------------------------------------------------------
-- Description: parallel to Serial Shift Register with Asynchronous Load and Clear
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003/04/21  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

-- Tri-statable parallel to serial shift register, with async. load and clear.
-- '1' on clr port sets all bits of internal register to zero. Output unaffected.
-- '1' on load port loads parallel data into internal register
-- '1' on oe port transfers internal bus contents to output pin one bit per
-- rising clock edge. Each output bit delayed by user-specified td.
-- To ensure proper operation, only one control pin should be active at a time

library IEEE;
use IEEE.std_logic_1164.all;

entity p2s_shift_reg is
  generic (
    td    :  time    := 0 ns;  -- Delay time for OE
    Nbits :  integer := 12     -- Size of bus         
    );
  port
    (
      bus_in  : in  std_logic_vector;   -- Input bus
      clk     : in  std_logic;          -- Shift clock
      oe      : in  std_logic;          -- Output enable
      ser_out : out std_logic := 'Z';   -- Output port
      load    : in  std_logic;          -- Parallel input load
      clr     : in  std_logic           -- Clear register
      );
end entity p2s_shift_reg;

architecture behavioral of p2s_shift_reg is
begin
  control_proc : process is
    variable bus_int : std_logic_vector(Nbits-1 downto 0);  -- Internal bus
  begin
    if (oe = '0' or oe = 'L') then
      ser_out   <= 'Z';                 -- If OE != 1, tri-state output
    end if;
    if (clr = '1' or clr = 'H') then
      bus_int      := (others => '0');  -- Set all input bits to zero
      wait on clr;                      -- No change until clr goes low
    elsif (load'event and (load = '1' or load = 'H')) then
      for i in Nbits-1 downto 0 loop
        bus_int(i) := bus_in(i);        -- Transfer input data to internal bus
      end loop;
    elsif (oe = '1' or oe = 'H') then   -- Shift data to output if OE enabled
      for i in Nbits-1 downto 0 loop
        wait until clk'event and (clk = '1' or clk = 'H');  -- One bit per clk rising edge
        ser_out <= bus_int(i) after td;  -- Shift out new bit on each clock
      end loop;
    end if;
    wait on load, clr, clk, oe;         -- Suspend process and await port activity
  end process;
end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------