-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
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-- notice that this model has been modified and the date of modification; and 
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-- conspicuous notice that this model is available from Mentor Graphics in its
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-------------------------------------------------------------------------------
-- File       : pattern_det.vhd
-- Author     : Mentor Graphics
-- Created    : 2003/04/21
-- Last update: 2003/04/23
-------------------------------------------------------------------------------
-- Description: Pattern Detection Device
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003/04/21  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------
-- This model ouputs a '1' when a user-specifiid bit pattern is encountered
-- Otherwise, it outputs a zero. Comparison is made on each rising clock edge.

library IEEE;
use IEEE.std_logic_1164.all;

entity pattern_det is
  generic (
    pattern  : std_logic_vector := "101010101010";
    Nbits    : integer          := 12
    );
  port
    (
      bus_in : in  std_logic_vector (0 to Nbits-1);
      clk    : in  std_logic;
      output : out std_logic := '0'  -- Initialize output to zero
      );
end entity pattern_det;

architecture simple of pattern_det is
begin
  enbl : process (bus_in, clk)          -- Sensitivity list
  begin
    if clk'event and clk = '1' then     -- Output updated on rising clock only
      if bus_in = pattern then          -- This is the user-defined bit pattern 
        output    <= '1';
      else output <= '0';
      end if;
    end if;
  end process;
end architecture simple;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
------------------------------------------------------------------------------