-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : s2p_shift_reg.vhd
-- Author     : Mentor Graphics
-- Created    : 2003/04/21
-- Last update: 2003/04/23
-------------------------------------------------------------------------------
-- Description: Serial to Parallel Shift Register with Asynchronous Load and Clear,
-- and Tri-State output.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003/04/21  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

-- Tri-statable serial to parallel shift register, with async. load and clear.
-- '1' on clr port sets all bits of internal register to zero. Output unaffected.
-- '1' on load port allows serial data to be shifted into register, one bit per
-- rising clock edge.
-- '1' on oe port transfers internal bus contents to output pins, after delay td.
-- To ensure proper operation, only one control pin should be active at a time.

library IEEE;
use IEEE.std_logic_1164.all;

entity s2p_shift_reg is
  generic (
    td    : time     := 0 ns;  -- Delay for OE
    --Nbits : integer  := 12  -- Size of bus
    );
  port
    (
      --bus_out : out std_logic_vector(Nbits-1 downto 0) := (others => 'Z');
      bus_out : out std_logic_vector(11 downto 0);
      clk     : in  std_logic;
      load    : in  std_logic;
      oe      : in  std_logic;
      ser_in  : in  std_logic;
      clr     : in  std_logic
      );
end entity s2p_shift_reg;

architecture behavioral of s2p_shift_reg is
  --signal bus_int : std_logic_vector(Nbits-1 downto 0);  -- Internal bus
  signal bus_int : std_logic_vector(11 downto 0);  -- Internal bus
begin
  control_proc : process is
    variable index : integer := 0;  -- Index determines which bit is updated
  begin
    if (oe = '0' or oe = 'L') then
      bus_out <= (others => 'Z');  -- Tri-state if oe != 1.
    end if;
    if (clr = '1' or clr = 'H') then
      bus_int <= (others => '0');          -- Set all internal output bits to zero
      --index := Nbits-1;                    -- Reset index to top of bus range
      index := 11;
      wait on clr;                         -- No change until clr goes low
    elsif (load = '1' or load = 'H') then  -- Load internal bus (bus_int)
      if (clk'event and clk = '1') then    -- Shift in bit on rising clock edge
        bus_int(index) <= ser_in;          -- Put input bit into internal bus
        index := index-1;                  -- Decrement index to address next bit
        if index = 0 then
          --index := Nbits-1;                -- Reset index if we reach bottom of range
          index := 11;
        end if;
      end if;
    elsif (oe'event and (oe = '1' or oe = 'H')) then  -- Place internal bus on output
      for i in Nbits-1 downto 0 loop
        bus_out(i)     <= bus_int(i) after td;        -- Load up the output bus
      end loop;
    end if;
    wait on load, clr, clk, oe;         -- Suspend process, await new control activity
  end process;
end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------