------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : sw_ctrl.vhd -- Author : Mentor Graphics -- Created : 2003-04-18 -- Last update: 2003-04-18 ------------------------------------------------------------------------------- -- Description: Switch controller with integer signal output ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003-04-18 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Notes: -- 1. Input switch position and time data in vector format. -- 2. Number of points in both vectors must be equal. -- 3. Use to drive EduLib multi-pole, multi-throw switch models. -- 4. Assign integer sw_pos values according to switch being used. ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- The MGC_AMS library contains a "conversion" package that includes the -- time_vector and integer_vector type definitions (currently pending IEEE -- approval). The source file (mgc_ams_additions.vhd) is located in the -- SystemVision install tree. library MGC_AMS; use MGC_AMS.conversion.all; entity sw_ctrl is generic ( sw_pos : integer_vector := (1, 2, 1, 2); --Sample position data format sw_time : time_vector := (0 ms, 1 ms, 2 ms, 3 ms) -- Sample time data format ); port ( signal output : out integer := 1); end entity sw_ctrl; ------------------------------------------------------------------------------- -- architecture definition ------------------------------------------------------------------------------- architecture ideal of sw_ctrl is signal out_signal : integer := 1; -- intermediate signal begin -- process to schedule output values set_output : process is variable count : integer := 0; begin wait until domain = time_domain; while count < sw_time'right loop out_signal <= sw_pos(count); -- set out_signal to current position wait for (sw_time(count + 1) - sw_time(count)); -- wait for next change count := count + 1; end loop; out_signal <= sw_pos(sw_pos'right); -- hold output at last value wait; -- forever end process set_output; output <= out_signal; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -------------------------------------------------------------------------------