------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. 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MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : sw_matrix.vhd -- Author : Mentor Graphics -- Created : 2003-04-18 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Electrical matrix switch ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003-04-18 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Notes: -- 1. Integer value on ctrl port determines switch position. -- 2. Use sw_ctrl.vhd model in SystemVision model library ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- Use IEEE natures and packages use IEEE.electrical_systems.all; entity sw_matrix is generic (r_open : resistance := 1.0e6; -- Open (off) resistances r_closed : resistance := 1.0e-3; -- Closed (on) resistances td_make : real := 1.0e-9; -- time to "make" contacts td_break : real := 1.1e-9); -- time to "break" contacts port (signal ctrl : in integer; terminal a1, a2, a3, b1, b2, b3 : electrical); end entity sw_matrix; architecture ideal of sw_matrix is signal r_siga1b1 : resistance := r_open; signal r_siga1b2 : resistance := r_open; signal r_siga1b3 : resistance := r_open; signal r_siga2b1 : resistance := r_open; signal r_siga2b2 : resistance := r_open; signal r_siga2b3 : resistance := r_open; signal r_siga3b1 : resistance := r_open; signal r_siga3b2 : resistance := r_open; signal r_siga3b3 : resistance := r_open; quantity v_a1b1 across i_a1b1 through a1 to b1; -- branch quantities quantity v_a1b2 across i_a1b2 through a1 to b2; quantity v_a1b3 across i_a1b3 through a1 to b3; quantity v_a2b1 across i_a2b1 through a2 to b1; quantity v_a2b2 across i_a2b2 through a2 to b2; quantity v_a2b3 across i_a2b3 through a2 to b3; quantity v_a3b1 across i_a3b1 through a3 to b1; quantity v_a3b2 across i_a3b2 through a3 to b2; quantity v_a3b3 across i_a3b3 through a3 to b3; quantity r_a1b1 : resistance; -- free quantities quantity r_a1b2 : resistance; quantity r_a1b3 : resistance; quantity r_a2b1 : resistance; quantity r_a2b2 : resistance; quantity r_a2b3 : resistance; quantity r_a3b1 : resistance; quantity r_a3b2 : resistance; quantity r_a3b3 : resistance; begin -- purpose: Detect Switch position and assign resistance value to r_sig -- type : combinational -- inputs : ctrl -- outputs: r_sig DetectPosition : process (ctrl) begin -- position 1 connects a1 to b1, a2 to b2 and a3 to b3 if (ctrl = 1) then r_siga1b1 <= r_closed; -- signal assignments r_siga1b2 <= r_open; r_siga1b3 <= r_open; r_siga2b1 <= r_open; r_siga2b2 <= r_closed; r_siga2b3 <= r_open; r_siga3b1 <= r_open; r_siga3b2 <= r_open; r_siga3b3 <= r_closed; -- position 2 connects a1 to b2, a2 to b1 and a3 to b3 elsif (ctrl = 2) then r_siga1b1 <= r_open; r_siga1b2 <= r_closed; r_siga1b3 <= r_open; r_siga2b1 <= r_closed; r_siga2b2 <= r_open; r_siga2b3 <= r_open; r_siga3b1 <= r_open; r_siga3b2 <= r_open; r_siga3b3 <= r_closed; -- position 3 connects a1 to b3, a2 to b1 and a3 to b2 elsif (ctrl = 3) then r_siga1b1 <= r_open; r_siga1b2 <= r_open; r_siga1b3 <= r_closed; r_siga2b1 <= r_closed; r_siga2b2 <= r_open; r_siga2b3 <= r_open; r_siga3b1 <= r_open; r_siga3b2 <= r_closed; r_siga3b3 <= r_open; -- position 4 connects a1 to b1, a2 to b3 and a3 to b2 elsif (ctrl = 4) then r_siga1b1 <= r_closed; r_siga1b2 <= r_open; r_siga1b3 <= r_open; r_siga2b1 <= r_open; r_siga2b2 <= r_open; r_siga2b3 <= r_closed; r_siga3b1 <= r_open; r_siga3b2 <= r_closed; r_siga3b3 <= r_open; -- position 5 connects a1 to b2, a2 to b3 and a3 to b1 elsif (ctrl = 5) then r_siga1b1 <= r_open; r_siga1b2 <= r_closed; r_siga1b3 <= r_open; r_siga2b1 <= r_open; r_siga2b2 <= r_open; r_siga2b3 <= r_closed; r_siga3b1 <= r_closed; r_siga3b2 <= r_open; r_siga3b3 <= r_open; else -- undefined positions set all resistances to r_open r_siga1b1 <= r_open; r_siga1b2 <= r_open; r_siga1b3 <= r_open; r_siga2b1 <= r_open; r_siga2b2 <= r_open; r_siga2b3 <= r_open; r_siga3b1 <= r_open; r_siga3b2 <= r_open; r_siga3b3 <= r_open; end if; end process DetectPosition; r_a1b1 == r_siga1b1'RAMP(td_break, td_make); -- use 'ramp attribute for r_a1b2 == r_siga1b2'RAMP(td_break, td_make); -- linear transition between r_a1b3 == r_siga1b3'RAMP(td_break, td_make); -- values r_a2b1 == r_siga2b1'RAMP(td_break, td_make); r_a2b2 == r_siga2b2'RAMP(td_break, td_make); r_a2b3 == r_siga2b3'RAMP(td_break, td_make); r_a3b1 == r_siga3b1'RAMP(td_break, td_make); r_a3b2 == r_siga3b2'RAMP(td_break, td_make); r_a3b3 == r_siga3b3'RAMP(td_break, td_make); v_a1b1 == r_a1b1*i_a1b1; v_a1b2 == r_a1b2*i_a1b2; v_a1b3 == r_a1b3*i_a1b3; v_a2b1 == r_a2b1*i_a2b1; v_a2b2 == r_a2b2*i_a2b2; v_a2b3 == r_a2b3*i_a2b3; v_a3b1 == r_a3b1*i_a3b1; v_a3b2 == r_a3b2*i_a3b2; v_a3b3 == r_a3b3*i_a3b3; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -------------------------------------------------------------------------------