| Name | Last modified | Size | Description | |
|---|---|---|---|---|
| Parent Directory | - | |||
| a2d_2thresholds.vhd | 24-Apr-2010 19:41 | 3.4K | ||
| adaptive_z.vhd | 24-Apr-2010 19:41 | 4.0K | ||
| clamp_iv.vhd | 24-Apr-2010 19:41 | 3.5K | ||
| clock_jitter.vhd | 24-Apr-2010 19:41 | 4.4K | ||
| clock_spreadspectrum.vhd | 24-Apr-2010 19:41 | 4.3K | ||
| cm_limiting_amplifier.vhd | 24-Apr-2010 19:41 | 4.2K | ||
| cml.vhd | 24-Apr-2010 19:41 | 3.8K | ||
| cml_pe_settable.vhd | 24-Apr-2010 19:41 | 5.2K | ||
| connector_rectwire_hhm.vhd | 24-Apr-2010 19:41 | 3.8K | ||
| connector_roundwire_hhm.vhd | 24-Apr-2010 19:41 | 3.8K | ||
| controller_totem.vhd | 24-Apr-2010 19:41 | 3.8K | ||
| current_multiplier.vhd | 24-Apr-2010 19:41 | 3.7K | ||
| data_logic_vector.vhd | 24-Apr-2010 19:41 | 3.0K | ||
| data_sampler.vhd | 24-Apr-2010 19:41 | 2.8K | ||
| data_time_vector.vhd | 24-Apr-2010 19:41 | 3.4K | ||
| dci.vhd | 24-Apr-2010 19:41 | 4.3K | ||
| decoupling_cap.vhd | 24-Apr-2010 19:41 | 4.4K | ||
| dig_prbs.vhd | 24-Apr-2010 19:41 | 3.5K | ||
| dig_prbs_jitter.vhd | 24-Apr-2010 19:41 | 4.8K | ||
| driver_cml_pe.vhd | 24-Apr-2010 19:41 | 7.9K | ||
| equalizer_set3bit.vhd | 24-Apr-2010 19:41 | 7.8K | ||
| phase_detector_hogge.vhd | 24-Apr-2010 19:41 | 4.0K | ||
| pkg_CRLC.vhd | 24-Apr-2010 19:41 | 3.2K | ||
| pkg_bondwire_hhm.vhd | 24-Apr-2010 19:41 | 4.3K | ||
| pre_emphasis_logic.vhd | 24-Apr-2010 19:41 | 5.0K | ||
| resistor_esl.vhd | 24-Apr-2010 19:41 | 2.8K | ||
| set_3bit.vhd | 24-Apr-2010 19:41 | 4.3K | ||
| switch_nonlinear.vhd | 24-Apr-2010 19:41 | 3.7K | ||
| switch_pwl_iv.vhd | 24-Apr-2010 19:41 | 4.0K | ||
| tline1.vhd | 24-Apr-2010 19:41 | 3.5K | ||
| tline2_sym.vhd | 24-Apr-2010 19:41 | 5.1K | ||
| vco_digital_out.vhd | 24-Apr-2010 19:41 | 3.4K | ||
| via_hhm.vhd | 24-Apr-2010 19:41 | 3.7K | ||