-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
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-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
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-- notice that this model has been modified and the date of modification; and 
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : clock_jitter.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Digital Clock Source with built-in edge jitter (Uniform Distribution)
--              Note: If two or more of these clocks are used in a circuit, user
--              must assign different "seed" values to have independent jitter behavior.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.math_real.all;

entity clock_jitter is
	generic (period     : time := 100 ps;	  -- Clock period
	         init_delay : time := 1 ps;       -- Initial delay to first rising edge
			 seed1_init : positive := 53;     -- Initial value of seed1. (1 <= seed1_init <= 2147483562)
			 seed2_init : positive := 632;    -- Initial value of seed2. (1 <= seed2_init <= 2147483562)
	         jitter_max : real := 5.0e-12);   -- Max. (peak) jitter from nominal clock edge
			                                  -- Must be < period/2.0
	port 	(clk_out : out std_logic);
end entity clock_jitter;


architecture behavioral of clock_jitter is

constant jitter_max_time : time := integer(jitter_max * 1.0e15) * 1 fs;

begin

CreateClock: process
variable out_variable : std_logic;
variable seed1 : positive := seed1_init;
variable seed2 : positive := seed2_init;
variable scale_jit_0_1 : real := 0.5;   -- Random number, jitter scale factor [0 to 1]
variable jitter_real : real := 0.0;	    -- Jitter offset of next edge (real, 0 -> 2.0*jitter_max)
variable jitter_time : time := 0.0 ps;  -- Jitter offset of next edge (time equivalent of jitter_real)
begin
	clk_out <= '0';
	wait until domain = time_domain;
	wait for init_delay;
	out_variable := '1';
	clk_out <= out_variable;
  	clk_loop : loop
		 -- Note: Can't have negative jitter delay, so must stop short of max jitter window 
		 wait for (period/2.0 -  jitter_max_time);			
			uniform(seed1, seed2, scale_jit_0_1);
			jitter_real := 2.0*jitter_max*scale_jit_0_1;
			jitter_time := integer(jitter_real * 1.0e15) * 1 fs;
			out_variable := not out_variable;
      		clk_out <= out_variable after jitter_time;
			wait for (jitter_max_time);
    end loop clk_loop;
end process CreateClock;

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------