-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : clock_spreadspectrum.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Digital Clock Source with Spread-Spectrum. Offset to the nominal
--              clock period is ramped from -1.0*ss_mag to +1.0*ss_mag and back,
--              every "ss_cycle_count" number of clock periods.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity clock_spreadspectrum is
  generic (period     : real		:= 1.0e-9;   -- Nominal clock period
		   ss_mag     : real		:= 20.0e-12; -- Spread-spectrum peak offset to period
		   ss_cycle_count : integer := 100);     -- Spread-spectrum repetition cycle in terms
		                                         -- of the number of fundamental clock periods
    port(
        clk_out : out std_logic);
end clock_spreadspectrum;

architecture ramped_period of clock_spreadspectrum is

  signal offset : real := 0.0;
  signal count : integer := 0;
  signal local_clk_out : std_logic := '1';
  signal nom_clk : std_logic := '1';
  constant rcount : real := real(ss_cycle_count);
  constant period_time : time := integer(period * 1.0e15) * 1 fs; 

begin

	Update_count : process
	begin
		wait for period_time;  
		if count < ss_cycle_count then
			count <= count + 1;
		else
			count <= 1;
		end if;
	end process Update_count;

	ComputeOffset: process
	begin
		wait on count;
		if real(count) <= rcount/4.0 then
			offset <= ss_mag*(real(count)/(rcount/4.0));
		elsif real(count) <= 3.0*rcount/4.0 then
			offset <= ss_mag*(1.0 - (real(count) - rcount/4.0)/(rcount/4.0));
		else
			offset <= ss_mag*(-1.0 + (real(count) - 3.0*rcount/4.0)/(rcount/4.0));
		end if;		
	end process ComputeOffset;

	GenerateClock: process
	begin
		local_clk_out <= not local_clk_out;
		wait for integer(((period + offset)/2.0)*1.0e15) * 1 fs;
	end process GenerateClock;

	clk_out <= local_clk_out;

	---------------------------------------------------------------------------
	Nominal_clock : process  -- Not used for spread-spectrum, just a reference.
	begin
		nom_clk <= not nom_clk;
	wait for period_time;
	end process Nominal_clock;

end ramped_period;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------