-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- notice that this model has been modified and the date of modification; and 
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-- conspicuous notice that this model is available from Mentor Graphics in its
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : cml.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Ideal Differential Current Model Logic (CML) Driver. Used in combination
--              with two external pull-up resistors connected to Vcc, where terminals 
--              out_p and out_n are attached to the low-side of these resistors. This model steers 
--              current "isource" from out_p or out_n to an internal ground. For logic input
--              d_input = '1', all of isource flows through out_n to internal ground, 
--              pulling the voltage at out_n down, below Vcc (because of i*R drop in external
--              resistor). Current flows through out_p to the internal ground when d_input = '0',
--              pulling the voltage at out_p down. Current switching time is specified by trans_time.        
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;

entity cml is
  generic (isource    : current    := 20.0e-3;
           trans_time : real       := 10.0e-12);

  port (d_input         : in std_logic;
        terminal out_p, out_n :    electrical);

end entity cml;


architecture ideal of cml is

  signal   k : real := 0.0;
  quantity v_p across i_p through out_p to electrical_ref;
  quantity v_n across i_n through out_n to electrical_ref;

begin

  input_state: process (d_input)
  begin
    if d_input = '1' then
      k <= 1.0;
    else
      k <= 0.0;
    end if;
  end process input_state;

  i_n == k'ramp(trans_time, trans_time)*isource;
  i_p == isource - i_n;

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------