-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- notice that this model has been modified and the date of modification; and 
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-- conspicuous notice that this model is available from Mentor Graphics in its
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : cml_pe_settable.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Differential Current-Mode Logic (CML) Driver with Pre-Emphasis (PE)
--              capability. Has 4-state settable PE current levels, controlled by the 
--              voltage applied to the two "pe_set" inputs, relative to threshold "thres".
--              This model is used in combination with two external pull-up resistors 
--              connected to Vcc, where terminals out_p and out_n are attached to the 
--              low-side of these resistors. This model steers the total current (base 
--              current plus instantaneous pre-emphasis current) from out_p or out_n to 
--              an internal ground. For logic input d_input = '1', all of the current flows 
--              through out_n to internal ground, pulling the voltage at out_n down, below 
--              Vcc (because of the i*R drop in external resistor). The current flows through 
--              out_p to the internal ground when d_input = '0', pulling the voltage at out_p 
--              down. Current switching time is specified by trans_time. 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;

entity cml_pe_settable is
  generic (ibase : real := 20.0e-3;       -- Base current level
           ipe_max  : real := 20.0e-3;    -- Maximum PE current, for pe_set inputs = ('1' '1')
		   trans_time : real := 10.0e-12; -- Transition time for current switch
		   thres : real := 1.0);		  -- Threshold voltage level for pe_set

  port (d_input, d_pe : in std_logic;
        terminal pe_set_msb, pe_set_lsb, out_p, out_n : electrical);

end entity cml_pe_settable;


architecture behavioral of cml_pe_settable is

  signal   k_p, k_n : real := 0.0;
  signal   pe_scale : real := 0.0;
  quantity v_p across i_p through out_p to electrical_ref;
  quantity v_n across i_n through out_n to electrical_ref;
  quantity v_msb across pe_set_msb to electrical_ref;
  quantity v_lsb across pe_set_lsb to electrical_ref;
  constant pe_ratio : real := ipe_max/ibase;

begin

  set_pe : process (v_msb'above(thres), v_lsb'above(thres))
  begin
    if v_msb'above(thres) and v_lsb'above(thres) then
      pe_scale <= 1.0;
    elsif v_msb'above(thres) and not v_lsb'above(thres) then
      pe_scale <= 0.666;
    elsif v_msb'above(thres) and v_lsb'above(thres) then
      pe_scale <= 0.333;
    else
	  pe_scale <= 0.0;
    end if;
  end process set_pe;

  input_state: process (d_input, d_pe)
  begin
    if d_input = '1' and d_pe = '1' then
      k_n <= 1.0 + pe_ratio*pe_scale;
	  k_p <= 0.0;
	elsif d_input = '1' and d_pe = '0' then
	  k_n <= 1.0;
	  k_p <= 0.0;
	elsif d_input = '0' and d_pe = '1' then
	  k_n <= 0.0;
	  k_p <= 1.0 + pe_ratio*pe_scale;
    else
      k_n <= 0.0;
	  k_p <= 1.0;
    end if;
  end process input_state;

  i_n == k_n'ramp(trans_time, trans_time)*ibase;
  i_p == k_p'ramp(trans_time, trans_time)*ibase;

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------