-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
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-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : dig_prbs.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Digital Pseudo-Random Bit Stream (PRBS) Data. 
--              Note: If two or more of these data sources are used in a circuit, user
--              must assign different "seed" values to have independent data sequences.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.math_real.all;

entity dig_prbs is
	generic (ui     : time := 100 ps);	      -- Data Unit Interval
	port 	(d_output : out std_logic);
end entity dig_prbs;

architecture behavioral of dig_prbs is
begin

CreateSequence: process
variable out_variable : std_logic;
variable seed1, seed2 : positive := 1;
variable set_value_0_1 : real := 0.5;   -- Random number to set output value [0 to 1]
begin
    uniform(seed1, seed2, set_value_0_1);
	if set_value_0_1 >= 0.5 then
	  out_variable := '1';
	else
	  out_variable := '0';
	end if;
	d_output <= out_variable;
	wait until domain = time_domain;
  	ui_loop : loop
		 wait for ui;			
			uniform(seed1, seed2, set_value_0_1);
			if set_value_0_1 >= 0.5 then
	  		  out_variable := '1';
			else
	  		  out_variable := '0';
			end if;
      		d_output <= out_variable;
    end loop ui_loop;
end process CreateSequence;

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------