------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. 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MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : equalizer_set3bit.vhd -- Author : Mentor Graphics -- Created : 2003-05-30 -- Last update: ------------------------------------------------------------------------------- -- Description: Complete Behavioral Equalizer Model. Has 3-bit input to set -- amount of equalizer boost. Differential CML input signal is -- split between a Boost Amplifier (Lead-Lag filter followed by -- a 2nd order Low-Pass filter) and a Flat Amplifier. The boost -- amplifier has a region of increasing gain with frequency, to -- compensate for frequency dependent losses typical in a PCB trace. -- The Boost and Flat Amplifier outputs are weighted based on the -- 3-bit settings (111 gives 100% boost, 000 gives 0% boost), and then -- summed to drive a current mode output limiting amplifier. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003-05-30 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.math_real.all; use IEEE.electrical_systems.all; entity equalizer_set3bit is generic (thres : real := 1.0; -- Threshold for settable boost state inputs R_cml_in : resistance := 50.0; -- CML input resistance R_cml_out : resistance := 50.0; -- CML output resistance Fp : real := 15.0e9; -- Boost amplifier pole frequency Fz : real := 1.5e9; -- Zero frequency Fp_lpf : real := 20.0e9; -- Double Pole Frequency for LPF [Hz] Q : real := 0.5; -- Quality factor of LPF i_max : current := 20.0e-3; -- Maximum current output i_gain : real := 40.0e-3); -- Output Amplifier current gain, (Amps./Volt) port( terminal v_sdi_p : electrical; -- Differential inputs (p and n) terminal v_sdi_n : electrical; terminal v_eq1 : electrical; -- Equalizer setting bits (v_eq3 is MSB, 111 = max. boost) terminal v_eq2 : electrical; terminal v_eq3 : electrical; terminal v_sdo_p : electrical; -- Differential outputs (p and n) terminal v_sdo_n : electrical; terminal v_vcc1 : electrical; -- Rail voltage for CML input terminal v_vcc2 : electrical; -- Rail voltage for CML output terminal v_gnd : electrical -- Ground pin ); end equalizer_set3bit; architecture behavioral of equalizer_set3bit is quantity vin_p across iin_p through v_sdi_p to v_vcc1; quantity vin_n across iin_n through v_sdi_n to v_vcc1; quantity vsdi_p across v_sdi_p to v_gnd; quantity vsdi_n across v_sdi_n to v_gnd; quantity v_sdi_diff : real; quantity v_leadlag_out : real; quantity v_boostamp_out : real; quantity veq1 across v_eq1 to Electrical_ref; quantity veq2 across v_eq2 to Electrical_ref; quantity veq3 across v_eq3 to Electrical_ref; quantity boost_scalefactor : real; quantity v_eq_sum : real; quantity i_p through v_sdo_p to v_gnd; quantity i_n through v_sdo_n to v_gnd; quantity vcml_p across icml_p through v_vcc2 to v_sdo_p; quantity vcml_n across icml_n through v_vcc2 to v_sdo_n; constant wp : real := math_2_pi*Fp; -- Pole freq (in radians) constant wz : real := math_2_pi*Fz; -- Zero freq (in radians) constant num : real_vector := (1.0, 1.0/wz); constant den : real_vector := (1.0, 1.0/wp); constant wp_lpf : real := math_2_pi*Fp_lpf; -- Frequency in Radians of LPF poles constant num_lpf : real_vector := (wp_lpf*wp_lpf, 0.0, 0.0); -- Numerator array (LPF) constant den_lpf : real_vector := (wp_lpf*wp_lpf, wp_lpf/Q, 1.0); -- Denominator array (LPF) begin -- Find the input CML currents iin_p * R_cml_in == vin_p; iin_n * R_cml_in == vin_n; -- Compute differential input voltage v_sdi_diff == vsdi_p - vsdi_n; -- Find output of boost amplifier (DC gain = 1.0) v_leadlag_out == v_sdi_diff'ltf(num, den); v_boostamp_out == v_leadlag_out'ltf(num_lpf, den_lpf); -- Compute settable boost gain. if veq3'above(thres) and veq2'above(thres) and veq1'above(thres) use boost_scalefactor == 1.0; elsif veq3'above(thres) and veq2'above(thres) and not veq1'above(thres) use boost_scalefactor == 0.857; elsif veq3'above(thres) and not veq2'above(thres) and veq1'above(thres) use boost_scalefactor == 0.714; elsif veq3'above(thres) and not veq2'above(thres) and not veq1'above(thres) use boost_scalefactor == 0.571; elsif not veq3'above(thres) and veq2'above(thres) and veq1'above(thres) use boost_scalefactor == 0.428; elsif not veq3'above(thres) and veq2'above(thres) and not veq1'above(thres) use boost_scalefactor == 0.286; elsif not veq3'above(thres) and not veq2'above(thres) and veq1'above(thres) use boost_scalefactor == 0.143; else boost_scalefactor == 0.0; end use; -- Sum the scaled outputs from the boost and the flat amplifier (flat amp. gain = 1.0) v_eq_sum == v_boostamp_out*boost_scalefactor + v_sdi_diff*(1.0 - boost_scalefactor); -- Find the current-mode limiting amplifier currents (i_p and i_n) if v_eq_sum'above(0.0) use if v_eq_sum'above(i_max/i_gain) use i_n == i_max; i_p == 0.0; else i_n == 0.5*(i_max + v_eq_sum*i_gain); i_p == 0.5*(i_max - v_eq_sum*i_gain); end use; else if not v_eq_sum'above(-1.0*i_max/i_gain) use i_n == 0.0; i_p == i_max; else i_n == 0.5*(i_max + v_eq_sum*i_gain); i_p == 0.5*(i_max - v_eq_sum*i_gain); end use; end use; break on v_eq_sum'above(i_max/i_gain); break on v_eq_sum'above(-i_max/i_gain); -- Solve for output CML currents icml_p * R_cml_out == vcml_p; icml_n * R_cml_out == vcml_n; end behavioral; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -------------------------------------------------------------------------------