-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
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-------------------------------------------------------------------------------
-- File       : phase_detector_hogge.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Phase Detector with digital inputs, analog output. Represents a
--              Hogge type phase detector, so it can be used as part of the PLL
--              for a clock and data recovery behavioral model. 
--              (Ref: IEEE Communications Magazine, August 2002: "Challenges in 
--              the Design of High-Speed Clock and Data Recovery Circuits", 
--              Behzad Razavi, University of California, Los Angeles)
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;

entity phase_detector_hogge is
	generic (vlow   : voltage := -1.0;      -- Output high voltage
             vhigh  : voltage :=  1.0;      -- Output low voltage
             t_ramp : real    := 10.0e-12); -- Ramp time from vlow to vhigh & vhigh to vlow
	port (
    	d_data, d_clk  : in  std_logic;
	    terminal a_out :  electrical);      -- Voltage equivalent of Y - X, range [-1,+1]
end entity phase_detector_hogge;

architecture behavioral of phase_detector_hogge is 
	signal d_b, d_a, d_y, d_x : std_logic := '0';
	signal vout_signal : real := 0.0;
    quantity vout across iout through a_out to electrical_ref;
begin  
	DFF: process (d_clk) is
	begin
    	if d_clk = '1' then
			d_b <= d_data;
		elsif d_clk = '0' then
			d_a <= d_b;
     	end if;
  	end process DFF;
 
	d_y <= d_data xor d_b;
	d_x <= d_b xor d_a;

	y_minus_x : process (d_y, d_x) is
	begin
		if d_y = '1' and d_x = '0' then
			vout_signal <= vhigh;
		elsif d_y = '0' and d_x = '1' then
			vout_signal <= vlow;
		else
			vout_signal <= (vhigh + vlow)/2.0;
		end if;
	end process y_minus_x;

	vout == vout_signal'ramp(t_ramp, t_ramp);

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------