------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : pkg_CRLC.vhd -- Author : Mentor Graphics -- Created : 2003-05-30 -- Last update: ------------------------------------------------------------------------------- -- Description: Package parasitic capacitance, resistance and inductance. -- Provides separate capacitance values for the die side and the package-pin side. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003-05-30 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.electrical_systems.all; entity pkg_CRLC is generic ( R : resistance := 0.5; -- Resistance value L : inductance := 1.0e-9; -- Inductance value C1 : capacitance := 0.1e-12; -- Capacitance value at p1 C2 : capacitance := 0.1e-12); -- Capacitance value at p2 port ( terminal p1, p2 : electrical); end entity pkg_CRLC; architecture behavioral of pkg_CRLC is quantity v across i through p1 to p2; quantity vc1 across ic1 through p1 to electrical_ref; quantity vc2 across ic2 through p2 to electrical_ref; begin v == L*i'dot + R*i; ic1 == C1*vc1'dot; ic2 == C2*vc2'dot; end architecture behavioral; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -------------------------------------------------------------------------------