------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : pkg_bondwire_hhm.vhd -- Author : Mentor Graphics -- Created : 2003-05-30 -- Last update: ------------------------------------------------------------------------------- -- Description: Bond wire model based on physical dimensions. Electrical characteristic -- formulas from "High Speed Digital System Design", by Hall, Hall and McCall, (pg. 114) -- Circuit topology: -- -- "p_die" ---------L1----L2----...----Ln------- "p_pkg" -- | | -- ----- ----- -- ----- C_die ----- C_pkg -- | | -- | | -- |-------------------------------| -- | -- "gnd" -- -- ... where L1, L2, ... Ln values are computed from physical dimensions of the bond wire ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003-05-30 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- Library IEEE; USE IEEE.math_real.ALL; USE IEEE.ELECTRICAL_SYSTEMS.ALL; ENTITY pkg_bondwire_hhm IS GENERIC ( d : real := 0.001; -- Diameter of bond wire (inches) h : real_vector; -- Set (array) of segment heights above the ground plane (inches) len : real_vector; -- Corresponding set (array) of wire lengths (inches) c_die : real := 1.0e-12; -- Effective capacitance of the die pad c_pkg : real := 1.0e-12 -- Effective capacitance of the package pad ); PORT ( TERMINAL p_die, p_pkg, gnd : electrical ); END ENTITY pkg_bondwire_hhm; ARCHITECTURE hhm OF pkg_bondwire_hhm IS function sum_inductors(diameter : in real; height, length : in real_vector) return real is variable L_sum : real := 0.0; variable i : integer := 0; begin while i <= height'right loop L_sum := L_sum + length(i)*(5.08e-9)*log(4.0*height(i)/diameter); i := i + 1; end loop; return L_sum; end function ; constant L_total : real := sum_inductors(d, h, len); -- Total via inductance quantity v across i through p_die to p_pkg; quantity v_die across i_c_die through p_die to gnd; quantity v_pkg across i_c_pkg through p_pkg to gnd; BEGIN v == L_total*i'dot; i_c_die == c_die*v_die'dot; i_c_pkg == c_pkg*v_pkg'dot; END ARCHITECTURE hhm; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -------------------------------------------------------------------------------