-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- notice that this model has been modified and the date of modification; and 
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-- conspicuous notice that this model is available from Mentor Graphics in its
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-------------------------------------------------------------------------------
-- File       : pre_emphasis_logic.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Simple Pre-Emphasis Controller State-Transition Logic. The d_base output 
--              takes the value of d_input on the rising edge of clk. The pre-emphasis
--              logic output d_pe goes to '1' only during the first bit after a 
--              transition. This model has four states: strong '1', weak '1', strong '0',
--              weak '0'. The d_pe output can be used to drive a second (supplementary)
--              output stage, or to control a behavioral driver output model built to accept
--              a pre-emphasis logic input.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY pre_emphasis_logic IS
    PORT (
          d_input : IN std_logic;
          clk : IN std_logic;
          d_base : OUT std_logic;
          d_pe : OUT std_logic);
END pre_emphasis_logic;

ARCHITECTURE state_transition OF pre_emphasis_logic IS

    TYPE program_logic_state IS (strong1, weak1, strong0, weak0);
    SIGNAL active_drive_state, next_drive_state : program_logic_state := weak0;
	signal clk_tick : std_logic := '0';  -- toggles on every '0' to '1' transition of clk

BEGIN 

set_next_state: PROCESS (d_input, clk_tick)
  BEGIN

    CASE active_drive_state IS
      WHEN strong1 =>
        IF ((d_input = '0')) THEN
          next_drive_state <= strong0;
        ELSIF ((d_input = '1')) THEN
          next_drive_state <= weak1;
        ELSE  -- Invalid input, stay in current state
          next_drive_state <= strong1;
        END IF;

      WHEN weak1 =>
        IF (d_input = '0') THEN
          next_drive_state <= strong0;
        ELSE
          next_drive_state <= weak1;
        END IF;

      WHEN strong0 =>
        IF ((d_input = '1')) THEN
          next_drive_state <= strong1;
		ELSIF ((d_input = '0')) THEN
          next_drive_state <= weak0;
        ELSE  -- Invalid input, stay in current state
          next_drive_state <= strong0;
        END IF;

	  WHEN weak0 =>
        IF (d_input = '1') THEN
          next_drive_state <= strong1;
        ELSE
          next_drive_state <= weak0;
        END IF;
    END CASE;
  END PROCESS set_next_state; 

update_outputs: PROCESS (active_drive_state) 
  BEGIN

    CASE active_drive_state IS
      WHEN strong1 =>
        d_base <= ('1');
        d_pe <= ('1');

      WHEN weak1 =>
        d_base <= ('1');
        d_pe <= ('0');

      WHEN strong0 =>
        d_base <= ('0');
        d_pe <= ('1');

	  WHEN weak0 =>
        d_base <= ('0');
        d_pe <= ('0');
    END CASE;
  END PROCESS update_outputs;
 
sync: PROCESS (clk)
  BEGIN
    IF (clk='1')  THEN 
        active_drive_state <= next_drive_state;
		clk_tick <= not clk_tick;
    END IF;
  END PROCESS sync;

END state_transition;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------