-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
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-- notice that this model has been modified and the date of modification; and 
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : set_3bit.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: General Purpose Settable Weighting Block, with 3-bit input.
--              Model reads the analog voltage value on the 3 inputs, and then
--              sets the two analog voltage outputs between [0.0 and 1.0]. The
--              outputs are quantized to 8 levels, v_increasing increases with
--              the input state, v_decreasing = 1.0 - v_increasing. The outputs
--              can be used, in combination with the multiplier models from the
--              ControlBlocks Library, to scale or "weight" other signals in
--              behavioral models. Set terminal "set3" is the MSB.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.math_real.all;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;

entity set_3bit is
  generic (
    thres : real := 1.0);               -- Threshold voltage to determine logic state
  port (
    terminal set1, set2, set3, v_increasing, v_decreasing :     electrical);  -- set3 is the MSB
end entity set_3bit;

architecture behavioral of set_3bit is
  quantity v1 across set1 to Electrical_ref;
  quantity v2 across set2 to Electrical_ref;
  quantity v3 across set3 to Electrical_ref;
  quantity vinc across iinc through v_increasing to Electrical_ref;
  quantity vdec across idec through v_decreasing to Electrical_ref;
begin

if v3'above(thres) and v2'above(thres) and v1'above(thres) use
  vinc == 1.0;
elsif v3'above(thres) and v2'above(thres) and not v1'above(thres) use
  vinc == 0.857;
elsif v3'above(thres) and not v2'above(thres) and v1'above(thres) use
  vinc == 0.714;
elsif v3'above(thres) and not v2'above(thres) and not v1'above(thres) use
  vinc == 0.571;
elsif not v3'above(thres) and v2'above(thres) and v1'above(thres) use
  vinc == 0.428;
elsif not v3'above(thres) and v2'above(thres) and not v1'above(thres) use
  vinc == 0.286;
elsif not v3'above(thres) and not v2'above(thres) and v1'above(thres) use
  vinc == 0.143;
else
  vinc == 0.0;
end use;

  vdec == 1.0 - vinc;

end behavioral;

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-- Copyright (c) 2003 Mentor Graphics Corporation
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