-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
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-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : switch_pwl_iv.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Piece-Wise Linear (PWL) i vs. v Switch. Can be used as a pull-up 
-- or pull-down element in a totem-pole drive stage configuration. User can enter
-- an arbitrary set of current vs. voltage data points to define the source impedance 
-- dependence on the operating point. Note: "vdata" points must be monotonically 
-- increasing.
-- Switching is controlled by a digital input, which causes a gain factor (k) to 
-- ramp between 0.0 and 1.0 during the transition time (t_ramp). This gain factor
-- scales the effective i vs. v relationship (k = 1 implies fully "ON"; 
-- k = 0 implies fully "Off", i.e. no current).
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;
Library MGC_AMS; 
use MGC_AMS.pwl_functions.all; 
 
entity switch_pwl_iv is
generic (	
	idata : real_vector;            -- i vs. v data
	vdata : real_vector;
	t_ramp : real := 100.0e-12	-- Switching time
	);
port (	
	d_input : in std_logic;   		-- Input logic signal
	terminal pos, neg :  electrical
	);
end entity switch_pwl_iv;

architecture behavioral of switch_pwl_iv is
	quantity v across i through pos to neg;
	signal k : real := 0.0;
	quantity k_ramp : real := 0.0;
	constant mono_data : boolean := monotonically_increasing(vdata);

begin

assert mono_data
	report "vdata must be monotonically increasing"
	severity error;

transition: process (d_input) is
begin
	if d_input = '1' then	
		k <= 1.0;
	else
		k <= 0.0;
	end if;		
end process transition;

	k_ramp == k'ramp(t_ramp, t_ramp);  -- Ramped coefficient (vs. time) to scale drive current
	
    i == k_ramp * pwl_dim1_extrap(v, vdata, idata);  -- Scale i vs. v characteristic by k_ramp

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------