-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
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-- notice that this model has been modified and the date of modification; and 
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : tline1.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Single conductor lossless transmission line, referenced to
-- electrical_ref (absolute ground).
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.electrical_systems.all;

entity tline1 is
	generic (
		z0  : real := 50.0;        -- Characteristic impedance
		td  : real := 1.0e-9       -- Propagation delay of line
	);
	port (
    	terminal p1, p2 : electrical);

end entity tline1;

architecture behavioral of tline1 is

  quantity v1 across i1 through p1 to ELECTRICAL_REF;
  quantity v2 across i2 through p2 to ELECTRICAL_REF;

  quantity v12_1 : voltage;  -- Voltage wave traveling from 1 toward 2, at 1
  quantity v21_1 : voltage;  -- Voltage wave traveling from 2 toward 1, at 1
  quantity v12_2 : voltage;  -- Voltage wave traveling from 1 toward 2, at 2
  quantity v21_2 : voltage;  -- Voltage wave traveling from 2 toward 1, at 2 

begin

  v12_2 == v12_1'delayed(td);  -- Voltage wave delay, 1 -> 2
  v21_1 == v21_2'delayed(td);  -- Voltage wave delay, 2 -> 1

  v1 == v12_1 + v21_1;         -- Voltage waves sum at 1
  i1 == v12_1/z0 - v21_1/z0;   -- Current waves subtract at 1
  v2 == v12_2 + v21_2;         -- Voltage waves sum at 2
  i2 == v21_2/z0 - v12_2/z0;   -- Current waves subtract at 2

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------