-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : tline2_sym.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Models a lossless, symmetric, two conductor transmission line.
--              Both conductors are  referenced to electrical_ref (absolute ground). 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;

entity tline2_sym is
	generic (
		z_odd  : real := 50.0;        -- Odd-mode characteristic impedance
		z_even : real := 50.0;        -- Even-mode characteristic impedance
		td_odd : real := 1.0e-9;      -- Odd-mode propagation delay of line
		td_even : real := 1.0e-9      -- Even-mode propagation delay of line
	);
	port (
    	terminal p1_1, p2_1, p1_2, p2_2 : electrical);  -- p1_1 and p2_1 are the conductors at the "1" end
		                                                -- p1_2 and p2_2 are the conductors at the "2" end

end entity tline2_sym;

architecture behavioral of tline2_sym is

  quantity v1_1 across i1_1 through p1_1 to ELECTRICAL_REF;
  quantity v2_1 across i2_1 through p2_1 to ELECTRICAL_REF;
  quantity v1_2 across i1_2 through p1_2 to ELECTRICAL_REF;
  quantity v2_2 across i2_2 through p2_2 to ELECTRICAL_REF; 

  quantity v_odd_12_1 : voltage;   -- Odd-mode voltage wave traveling from 1 toward 2, at 1
  quantity v_even_12_1 : voltage;  -- Even-mode voltage wave traveling from 1 toward 2, at 1
  quantity v_odd_21_1 : voltage;   -- Odd-mode voltage wave traveling from 2 toward 1, at 1
  quantity v_even_21_1 : voltage;  -- Even-mode voltage wave traveling from 2 toward 1, at 1
  quantity v_odd_12_2 : voltage;   -- Odd-mode voltage wave traveling from 1 toward 2, at 2
  quantity v_even_12_2 : voltage;  -- Even-mode voltage wave traveling from 1 toward 2, at 2
  quantity v_odd_21_2 : voltage;   -- Odd-mode voltage wave traveling from 2 toward 1, at 2
  quantity v_even_21_2 : voltage;  -- Even-mode voltage wave traveling from 2 toward 1, at 2

begin

  v_odd_12_2 == v_odd_12_1'delayed(td_odd);     -- Mode voltage waves delayed by modal td
  v_even_12_2 == v_even_12_1'delayed(td_even); 
  v_odd_21_1 == v_odd_21_2'delayed(td_odd);     
  v_even_21_1 == v_even_21_2'delayed(td_even);  

  v1_1 == MATH_1_OVER_SQRT_2*(v_odd_12_1 + v_odd_21_1 + v_even_12_1 + v_even_21_1);  
  v2_1 == MATH_1_OVER_SQRT_2*(-1.0*(v_odd_12_1 + v_odd_21_1) + v_even_12_1 + v_even_21_1);
  v1_2 == MATH_1_OVER_SQRT_2*(v_odd_12_2 + v_odd_21_2 + v_even_12_2 + v_even_21_2);
  v2_2 == MATH_1_OVER_SQRT_2*(-1.0*(v_odd_12_2 + v_odd_21_2) + v_even_12_2 + v_even_21_2);
  
  i1_1 == MATH_1_OVER_SQRT_2*((v_odd_12_1 - v_odd_21_1)/z_odd + (v_even_12_1 - v_even_21_1)/z_even);
  i2_1 == MATH_1_OVER_SQRT_2*(-1.0*(v_odd_12_1 - v_odd_21_1)/z_odd + (v_even_12_1 - v_even_21_1)/z_even);
  i1_2 == MATH_1_OVER_SQRT_2*((v_odd_21_2 - v_odd_12_2)/z_odd + (v_even_21_2 - v_even_12_2)/z_even);
  i2_2 == MATH_1_OVER_SQRT_2*(-1.0*(v_odd_21_2 - v_odd_12_2)/z_odd + (v_even_21_2 - v_even_12_2)/z_even);

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------