------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : vco_digital_out.vhd -- Author : Mentor Graphics -- Created : 2003-05-30 -- Last update: ------------------------------------------------------------------------------- -- Description: Voltage Controlled Oscillator (VCO) with digital output state. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003-05-30 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.electrical_systems.all; entity vco_digital_out is generic (fmax : real := 2.7e9; -- Frequency when v_input = vmax fmin : real := 2.3e9; -- Frequency when v_input = vmin vmax : real := 1.0; -- Input voltage for fmax vmin : real := -1.0); -- Input voltage for fmin port (d_out : out std_logic; -- Digital output terminal v_input : electrical); -- Input control (voltage) end entity vco_digital_out; architecture behavioral of vco_digital_out is quantity period : real; quantity v across v_input to electrical_ref; constant gain : real := (fmax - fmin)/(vmax - vmin); begin CreateEvent : process begin d_out <= '0'; wait until domain = time_domain; loop d_out <= '0'; wait for period/2.0; d_out <= '1'; wait for period/2.0; end loop; end process CreateEvent; period == 1.0/((v - vmin)*gain + fmin); end architecture behavioral; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -------------------------------------------------------------------------------