-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : via_hhm.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Via model based on physical dimensions. Electrical characteristic 
-- formulas from "High Speed Digital System Design", by Hall, Hall and McCall, (pg. 103-104)
-- Circuit topology:
--
--  "v1" -------L------- "v2"
--          |       |
--         C/2       C/2
--          |       |
--          ---------
--              |
--            "vref"
--
--  ... where L and C values are computed from physical dimensions of the via
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

Library IEEE;
USE IEEE.math_real.ALL;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;

ENTITY via_hhm IS 
  GENERIC (
  	d1 : real	:= 0.028;		-- Diameter of via pad (inches)
	d2 : real 	:= 0.05;		-- Diameter of anti-via pad (inches)
    t : real  	:= 0.063;		-- Thickness of the PCB
	epsr : real	:= 4.7;			-- Relative dielectric constant of the PCB material
    h : real  	:=  0.063; 		-- Height of the via
	d : real	:= 0.016		-- Diameter of the via
	);
  PORT (
    TERMINAL v1, v2, vref : electrical
	);
END ENTITY via_hhm;

ARCHITECTURE hhm OF via_hhm IS
	constant c_via : real := 1.41e-12*epsr*t*d1/(d2 - d1);		-- Total via capacitance
	constant l_via : real := 5.08e-9*h*(log(4.0*h/d) + 1.0);	-- Total via inductance
	quantity v12 across i12 through v1 to v2;
	quantity v1ref across i1ref through v1 to vref;
	quantity v2ref across i2ref through v2 to vref;
BEGIN
  	v12 == l_via*i12'dot;
	i1ref == (c_via/2.0)*v1ref'dot;
	i2ref == (c_via/2.0)*v2ref'dot;
END ARCHITECTURE hhm;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------