-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
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-------------------------------------------------------------------------------
-- File       : transformer.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/06/16
-- Last update: 2003-05-13
-------------------------------------------------------------------------------
-- Description: Ideal linear transformer (1 primary and 1 secondary winding)
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/06/16  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

library IEEE;
use ieee.math_real.all;
-- Use IEEE natures and packages
use IEEE.electrical_systems.all;

entity transformer is

  generic (
    rp : resistance;      -- Primary winding resistance [Ohms]
    rs : resistance;      -- Secondary winding resistance [Ohms]
    lp : inductance;      -- Primary inductance [Henrys]
    ls : inductance;      -- Secondary inductance [Henrys] 
    k  : real := 1.0);    -- coupling coefficient 

  port (terminal
        p1,                             -- Primary terminal 1
        p2,                             -- Primary terminal 2
        s1,                             -- Secondary terminal 1
        s2 : electrical);               -- Secondary terminal 2

end entity transformer;

-------------------------------------------------------------------------------
-- Ideal architecture
-------------------------------------------------------------------------------
architecture ideal of transformer is

  constant m : real := k * sqrt(lp * ls);  -- Mutual inductance
  quantity vpri across ipri through p1 to p2;
  quantity vsec across isec through s1 to s2;

begin
  vpri == ipri * rp + lp * ipri'dot + m * isec'dot;
  vsec == isec * rs + m * ipri'dot + ls * isec'dot;

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------