-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
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-- compilations distributed in accordance with Section (d) of this license 
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-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : a2d_nbit.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/12/03
-- Last update: 2003-05-13
-------------------------------------------------------------------------------
-- Description: Variable-bit A/D Converter 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/12/03  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.electrical_systems.all;

entity a2d_nbit is
  generic (
    Vmax  : voltage    := 5.0;             -- ADC's maximum range
    Nbits : integer := 10;              -- number bits in ADC's output
    delay : time    := 10 us            -- ADC's conversion time
    );

  port (
    signal   start : in  std_logic;     -- Start signal
    signal   clk   : in  std_logic;     -- Strobe clock
    signal   oe    : in  std_logic;     -- Output enable
    terminal ain   :     electrical;    -- ADC's analog input terminal
    signal   eoc   : out std_logic := '0';  -- End Of Conversion pin
    signal   dout  : out std_logic_vector(0 to (Nbits-1)));  -- Digital output
end entity a2d_nbit;

-------------------------------------------------------------------------------
--  
-- Successive Approximation Register (SAR) Architecture
--
--This is a VHDL-AMS model of a simple analog to digital converter. The model
--describes the general behavior of A/D converters for system level design and
--verification.
--The format of the digital output is binary coding.
--
--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
-------------------------------------------------------------------------------
architecture sar of a2d_nbit is
  type states is (input, convert, output);  -- Three states of A2D Conversion
  constant bit_range : integer := Nbits-1;  -- Bit range for dtmp and dout
  quantity Vin across Iin through ain to electrical_ref;  -- ADC's input branch

begin
  sa_adc : process
    variable thresh  : voltage    := Vmax;  -- Threshold to test input voltage
                                         -- against
    variable Vtmp    : voltage;          -- Snapshot of input voltage when
                                         -- conversion starts
    variable dtmp    : std_logic_vector(0 to (Nbits-1));  -- Temp. output data
    variable status  : states  := input; -- Begin with "input" CASE 
    variable bit_cnt : integer := Nbits -1;

  begin
    case status is
      when input   =>              -- Read input voltages when start goes high
        wait on start until start = '1' or start = 'H';
        thresh          := Vmax;
        Vtmp            := Vin;
        eoc             <= '0';
        status          := convert;     -- Go to convert state
      when convert =>             -- Begin successive approximation conversion
        thresh          := thresh / 2.0;  -- Get value of MSB
        wait on clk until clk = '1' or clk = 'H';
        if Vtmp > thresh then
          dtmp(bit_cnt) := '1';
          Vtmp          := Vtmp - thresh;
        else
          dtmp(bit_cnt) := '0';
        end if;
        bit_cnt         := bit_cnt - 1;
        if (bit_cnt + 1) < 1 then
          status        := output;      -- Go to output state
        end if;
      when output  =>  -- Wait for output enable, then put data on output pins
        eoc             <= '1' after delay;
        wait on oe until oe = '1' or oe = 'H';
        for i in bit_range downto 0 loop
          dout(i)       <= dtmp(i);
        end loop;
        wait on oe until oe = '0' or oe = 'L';  -- Hi Z when OE is low
        for i in bit_range downto 0 loop
          dout          <= "ZZZZZZZZZZ";
        end loop;
        bit_cnt         := bit_range;
        status          := input;       -- Set up for next conversion
    end case;
  end process sa_adc;

  Iin == 0.0;                           -- Ideal input draws no current

end architecture sar;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------