-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
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-------------------------------------------------------------------------------
-- File       : d2a_bit.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/06/16
-- Last update: 2003-05-13
-------------------------------------------------------------------------------
-- Description: Ideal one bit D/A converter
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/06/16  1.0         Mentor Graphics     Created
-- 2001/06/16  1.1         Mentor Graphics     Added t_ramp parameter
-------------------------------------------------------------------------------

library IEEE;
use IEEE.electrical_systems.all;
use IEEE.std_logic_1164.all;

entity d2a_bit is
  generic (vlow   : voltage := 0.0;     -- output high voltage
           vhigh  : voltage := 5.0;     -- output low voltage
           t_ramp : real    := 1.0e-9); -- Ramp time from vlow to vhigh
                                        -- and vhigh to vlow
  
  port (D : in std_logic;               -- digital (std_logic) intout
        terminal A :  electrical);      -- analog (electrical) output
end entity d2a_bit;

-------------------------------------------------------------------------------
-- Ideal architecture
-------------------------------------------------------------------------------
architecture ideal of d2a_bit is
  
  quantity vout across iout through A to electrical_ref;
  signal   vin : voltage := 0.0;

begin
  vin  <= vhigh when D = '1' else vlow;
  -- Use 'RAMP for discontinuous signal
  vout == vin'ramp(t_ramp);

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------